Design and Power-Performance Optimization of A Low Leakage Serial CAM by using DTCMOS Technique and Transistor Stacks

The Content Addressable Memory (CAM) is a class of memory that allows access by data instead of by physical address. On a read access to a CAM, embedded into a processor cache, each word is compared in a broadcast mode, to see if it matches the requested data; thus requiring only one access. Due to their parallel pattern matching property, CAMs are gaining increasing importance over Random Access Memory (RAM) in recent years, though design complexity and power consumption continue to remain the major drawbacks. The challenge in the design of a CAM cell is to reduce leakage power in its compare circuitry without sacrificing the speed. This paper describes a novel high-performance low power design of Serial CAM block using Dual-Threshold CMOS (DTCMOS) technique, Transmission Gates (TG), Transistor Stacks and an efficient Match Adaptive Architecture. In this design, for high speed and low power operation, we have used four separate, though not independent techniques. Replacing pass transistors by TG, including transistor stacks in the compare circuitry and assigning appropriate threshold voltages with dual threshold technique have been found to reduce the Power Delay Product (PDP) of the basic serial CAM cell by as much as up to 30%. Switching to a unique Match Adaptive Architecture further improves this Power-Performance of the CAM block significantly as compared to the conventional configuration. Index Terms ─ Stack Transistor, Dual Threshold CMOS, TG, PDP, Match Adaptive Architecture